This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications.

翻译：本文提出了一种结合符号聚焦压缩器的近似有符号乘法器架构，专为机器学习和信号处理中的边缘检测应用而设计。该乘法器包含两种类型的符号聚焦压缩器：A + B + C + 1 和 A + B + C + D + 1。设计中同时采用了精确和近似的压缩器，重点在于高效处理常数"1"和负部分积，这些在有符号乘法器的部分积矩阵中频繁出现。为了进一步提升效率，部分积矩阵的低 N - 1 列被截断，并辅以误差补偿机制。实验结果表明，与现有最佳乘法器相比，所提出的8位近似乘法器在功率延迟积上降低了29.21%，在功耗上降低了14.39%。所提出的乘法器被集成到一个自定义卷积层中并执行边缘检测，证明了其在现实应用中的实用性。