Could information about future incoming packets be used to build more efficient CPU-based packet processors? Can such information be obtained accurately? This paper studies novel packet processing architectures that receive external hints about which packets are soon to arrive, thus enabling prefetching into fast cache memories of the state needed to process them, just-in-time for the packets' arrival. We explore possible approaches to (i) obtain such hints either from network devices or the end hosts in the communication and (ii) use these hints to better utilize cache memories. We show that such information (if accurate) can improve packet processing throughput by at least 50%.

翻译：能否利用未来到达数据包的信息来构建更高效的基于CPU的数据包处理器？此类信息能否被准确获取？本文研究了一种新型数据包处理架构，该架构接收关于即将到达数据包的外部提示，从而能够在数据包到达前即时将处理所需状态预取至高速缓存中。我们探讨了两种可能途径：(i) 从网络设备或通信终端主机获取此类提示；(ii) 利用这些提示实现缓存资源的优化利用。研究表明，此类信息（若准确）可将数据包处理吞吐量提升至少50%。