Viterbi decoders are widely used in communication systems, natural language processing (NLP), and other domains. While Viterbi decoders are compute-intensive and power-hungry, we can exploit approximations for early design space exploration (DSE) of trade-offs between accuracy, power, and area. We present Locate, a DSE framework that uses approximate adders in the critically compute and power-intensive Add-Compare-Select Unit (ACSU) of the Viterbi decoder. We demonstrate the utility of Locate for early DSE of accuracy-power-area trade-offs for two applications: communication systems and NLP, showing a range of pareto-optimal design configurations. For instance, in the communication system, using an approximate adder, we observe savings of 21.5% area and 31.02% power with only 0.142% loss in accuracy averaged across three modulation schemes. Similarly, for a Parts-of-Speech Tagger in an NLP setting, out of 15 approximate adders, 7 report 100% accuracy while saving 22.75% area and 28.79% power on average when compared to using a Carry-Lookahead Adder in the ACSU. These results show that Locate can be used synergistically with other optimization techniques to improve the end-to-end efficiency of Viterbi decoders for various application domains.

翻译：维特比解码器广泛应用于通信系统、自然语言处理等领域。尽管维特比解码器计算密集且功耗较高，但我们可以利用近似方法进行早期设计空间探索（DSE），以权衡精度、功耗与面积。我们提出Locate框架，该框架在维特比解码器计算与功耗最为关键的加-比较-选择单元（ACSU）中使用近似加法器，实现早期DSE。我们通过通信系统和自然语言处理两类应用，展示了Locate在精度-功耗-面积权衡早期DSE中的实用性，获得一系列帕累托最优设计配置。例如，在通信系统中，使用近似加法器时，三种调制方案平均仅损失0.142%精度，却节省了21.5%面积和31.02%功耗。类似地，在自然语言处理的词性标注任务中，15种近似加法器中有7种在ACSU中相比于进位选择加法器保持100%精度，同时平均节省22.75%面积和28.79%功耗。这些结果表明，Locate可与其他优化技术协同使用，以提升维特比解码器在不同应用领域的端到端效率。