On modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous analytical placers. Moreover, general timing-driven placement algorithms are facing challenges when handling real-world application design and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an open-source comprehensive timing-driven analytical mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado. Standing upon the shoulders of AMF-Placer 1.0, AMFPlacer 2.0 is equipped with a series of new techniques for timing optimization, including a simple but effective timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timingdriven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools.

翻译：在现代现场可编程门阵列(FPGA)上，设计的某些关键路径部分在综合过程中可能预先组织成多个多单元宏模块。这些具有形状和资源约束的可移动宏模块给FPGA设计带来了具有挑战性的混合尺寸布局问题，而先前的解析布局器无法解决此问题。此外，通用时序驱动布局算法在处理实际应用设计和超大规模FPGA架构时正面临挑战。本文提出AMF-Placer 2.0，这是一个开源的综合时序驱动混合尺寸FPGA布局器，支持FPGA上异构资源（如LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM）的混合尺寸布局，并提供了与Xilinx Vivado的接口。AMF-Placer 2.0站在AMF-Placer 1.0的基础上，配备了一系列时序优化新技术，包括简单高效的时序模型、布局阻塞感知的锚点插入、WNS感知的时序驱动二次布局以及扇区引导的详细布局。基于一套面向Xilinx Ultrascale FPGA的最新大规模开源多领域基准测试集，实验结果表明：AMF-Placer 2.0实现的关键路径延迟分别比商业工具Xilinx Vivado 2020.2和2021.2平均高出2.2%和0.59%。同时，AMF-Placer 2.0布局过程的平均运行时间分别比Xilinx Vivado 2020.2和2021.2高14%和8.5%。尽管受限于缺乏器件的精确时序模型、设计层次结构信息和准确布线反馈，AMF-Placer 2.0仍是首个能够处理包含多种FPGA资源的实际复杂设计时序驱动混合尺寸布局的开源布局器，并达到了与最新商业工具可比较的质量。