Reconfigurable intelligent surface (RIS) is an emerging technology allowing to control the propagation environment in wireless communications. Recently, beyond diagonal RIS (BD-RIS) has been proposed to reach higher performance than conventional RIS, at the expense of higher circuit complexity. Multiple BD-RIS architectures have been developed with the goal of reaching a favorable trade-off between performance and circuit complexity. However, the fundamental limits of this trade-off are still unexplored. In this paper, we fill this gap by deriving the expression of the Pareto frontier for the performance-complexity trade-off in BD-RIS. Additionally, we characterize the optimal BD-RIS architectures reaching this Pareto frontier.

翻译：可重构智能表面（RIS）是一种新兴技术，可用于控制无线通信中的传播环境。近期，为达到比传统RIS更高的性能，人们提出了超越对角线RIS（BD-RIS），但代价是电路复杂度更高。为实现性能与电路复杂度之间的有利权衡，已开发出多种BD-RIS架构。然而，该权衡的基本极限仍未被探索。本文通过推导BD-RIS中性能-复杂度权衡的帕累托前沿表达式，填补了这一空白。此外，我们还刻画了能达到该帕累托前沿的最优BD-RIS架构。