The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of logic gates. Natural causes or soft errors in digital design could cause some of these gates to malfunction in the field, which could cause the multiplier to produce incorrect outputs. To ensure that they are not susceptible to error, it is crucial to use a finite field multiplier implementation that is effective and has a high fault detection capability. In this paper, we propose a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), where the proposed method aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation which is favored in resource constrained applications such as smart cards. The proposed method is based on BCH error correction codes, with an area-delay efficient architecture. The experimental results show that for 45-bit multiplier with 5-bit errors the proposed error detection and correction architecture results in 37% and %49 reduction in critical path delay with compared to the existing method in [18]. Moreover, the area overhead for 45-bit multiplier with 5 errors is within 80% which is significantly lower than the best existing BCH based fault detection method in finite field multiplier [18].

翻译：有限域乘法器广泛应用于当今众多先进数字系统中，其比特并行运算的硬件实现可能需要数百万个逻辑门。数字设计中的自然原因或软错误可能导致部分逻辑门在现场发生故障，进而使乘法器输出错误结果。为确保系统不易受错误影响，采用兼具高效性与高故障检测能力的有限域乘法器实现方案至关重要。本文针对基于GF(2m)的最新比特并行多项式基乘法器，提出一种新颖的故障检测方案，旨在实现有限域乘法器高故障检测性能的同时，保持低复杂度实现（该特性尤其适用于智能卡等资源受限应用）。所提方法基于BCH纠错码，并采用面积-延迟高效架构。实验结果表明，对于具有5位错误的45位乘法器，与现有文献[18]方法相比，所提错误检测与校正架构能使关键路径延迟降低37%和49%。此外，在45位乘法器含5个错误的情况下，面积开销控制在80%以内，显著低于现有基于BCH的有限域乘法器最优故障检测方法[18]。