Floorplanning is a critical early stage of VLSI physical design, and its quality directly impacts interconnect wirelength, chip performance, and downstream design efficiency. This article presents a multi-stage fixed-outline floorplanning framework that combines non-convex and convex optimization. The framework operates in three successive phases. In the initial floorplanning phase, a quadratic placement optimizes module connectivity to produce a topology-aware starting configuration with strong net clustering, albeit with significant module overlaps. In the global floorplanning phase, Adam-based projected gradient method is employed to solve non-convex optimization that minimizes wirelength and overlap. In the legalization phase, a log-transformed model exploiting horizontal and vertical constraint graphs eliminates residual overlaps under a convex formulation. Experiments on the MCNC, GSRC and HB+ benchmarks demonstrate that the framework achieves state-of-the-art wirelength quality, reducing average HPWL by at least 1\% and 5\% compared to state-of-the-art floorplanners on tested benchmarks.

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