Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection. In this paper, we investigate how to maximize the composability and scalability of an FPGA-based streaming ensemble anomaly detector (fSEAD). To achieve this, we propose a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors. Our proof-of-concept design supports three state-of-the-art anomaly detection algorithms: Loda, RS-Hash and xStream. Each algorithm is scalable, meaning multiple instances can be placed within a pblock to improve performance. Moreover, fSEAD is implemented using High-level synthesis (HLS), meaning further custom anomaly detectors can be supported. Pblocks are interconnected via an AXI-switch, enabling them to be composed in an arbitrary fashion before combining and merging results at run-time to create an ensemble that maximizes the use of FPGA resources and accuracy. Through utilizing reconfigurable Dynamic Function eXchange (DFX), the detector can be modified at run-time to adapt to changing environmental conditions. We compare fSEAD to an equivalent central processing unit (CPU) implementation using four standard datasets, with speed-ups ranging from $3\times$ to $8\times$.

翻译：机器学习集成通过组合多个基模型以产生更精确的输出，可应用于包括异常检测在内的多种机器学习问题。本文研究了如何最大化基于FPGA的流式集成异常检测器（fSEAD）的可组合性与可扩展性。为此，我们提出了一种灵活的计算架构，该架构由多个部分可重配置区域（pblock）构成，每个区域均实现异常检测器。我们的概念验证设计支持三种前沿异常检测算法：Loda、RS-Hash与xStream。每种算法均具备可扩展性，即单个pblock内可部署多个算法实例以提升性能。此外，fSEAD采用高层次综合（HLS）实现，这意味着可进一步支持定制化异常检测器。各pblock通过AXI交换机互连，使其能够在运行时以任意方式组合，并在结果融合前构建集成系统，从而最大化FPGA资源利用率与检测精度。通过利用可重配置动态功能交换（DFX），检测器可在运行时动态调整以适应环境变化。我们在四个标准数据集上将fSEAD与等效的中央处理器（CPU）实现进行对比，其加速比达到$3\times$至$8\times$。