Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.

翻译：电路设计中的自动晶体管尺寸优化仍是一项艰巨挑战。尽管贝叶斯优化（BO）已取得显著成功，但其具有电路特异性，限制了设计知识的积累与迁移以应用于更广泛场景。本文提出：（1）高效自动核构建方法；（2）首个面向不同电路与工艺节点的BO迁移学习框架；（3）选择性迁移学习机制以确保仅利用有效知识。这三个创新组件被集成至基于多目标采集集成（MACE）的BO中，形成知识对齐与迁移优化（KATO），实现了最先进的性能：相比基线方法，仿真成本最高降低2倍，设计质量提升1.2倍。