In this paper, we present a new analytical 3D placement framework with a bistratal wirelength model for F2F-bonded 3D ICs with heterogeneous technology nodes based on the electrostatic-based density model. The proposed framework, enabled GPU-acceleration, is capable of efficiently determining node partitioning and locations simultaneously, leveraging the dedicated 3D wirelength model and density model. The experimental results on ICCAD 2022 contest benchmarks demonstrate that our proposed 3D placement framework can achieve up to 6.1% wirelength improvement and 4.1% on average compared to the first-place winner with much fewer vertical interconnections and up to 9.8x runtime speedup. Notably, the proposed framework also outperforms the state-of-the-art 3D analytical placer by up to 3.3% wirelength improvement and 2.1% on average with up to 8.8x acceleration on large cases using GPUs.

翻译：本文提出一种基于静电密度模型的、面向异构工艺节点F2F键合三维集成电路的新型解析式三维布局框架。该框架通过GPU加速，利用专用三维线长模型和密度模型，能够同时高效确定节点划分与位置。在ICCAD 2022竞赛基准测试上的实验结果表明，与一等奖得主相比，所提出的三维布局框架在显著减少垂直互连数量的情况下，可实现最高6.1%（平均4.1%）的线长改善，并达到最高9.8倍的运行加速比。值得注意的是，在大规模案例中，该框架相较于最先进的三维解析布局器，在GPU上可实现最高3.3%（平均2.1%）的线长改善和最高8.8倍的加速比。