Neural interfaces read the activity of biological neurons to help advance the neurosciences and offer treatment options for severe neurological diseases. The total number of neurons that are now being recorded using multi-electrode interfaces is doubling roughly every 4-6 years \cite{Stevenson2011}. However, processing this exponentially-growing data in real-time under strict power-constraints puts an exorbitant amount of pressure on both compute and storage within traditional neural recording systems. Existing systems deploy various accelerators for better performance-per-watt while also integrating NVMs for data querying and better treatment decisions. These accelerators have direct access to a limited amount of fast SRAM-based memory that is unable to manage the growing data rates. Swapping to the NVM becomes inevitable; however, naive approaches are unable to complete during the refractory period of a neuron -- i.e., a few milliseconds -- which disrupts timely disease treatment. We propose co-designing accelerators and storage, with swapping as a primary design goal, using theoretical and practical models of compute and storage respectively to overcome these limitations.

翻译：神经接口通过读取生物神经元的活动，有助于推动神经科学的发展，并为严重神经系统疾病提供治疗方案。目前使用多电极接口记录的神经元总数大约每4-6年翻一番 \cite{Stevenson2011}。然而，在严格的功耗限制下实时处理这些呈指数级增长的数据，给传统神经记录系统的计算和存储带来了巨大压力。现有系统部署了各种加速器以提高能效，同时集成非易失性存储器（NVM）以支持数据查询和优化治疗决策。这些加速器可直接访问有限的基于SRAM的高速存储器，但这类存储器无法应对日益增长的数据速率。将数据交换至NVM变得不可避免；然而，简单的方法无法在神经元的不应期（即几毫秒内）完成交换，从而延误了及时治疗。我们提出协同设计加速器与存储器，将数据交换作为核心设计目标，分别利用计算与存储的理论模型和实际模型来克服这些限制。