Number Theoretic Transform (NTT) is the most essential component for polynomial multiplications used in lattice-based Post-Quantum Cryptography (PQC) algorithms such as Kyber, Dilithium, NTRU etc. However, side-channel attacks (SCA) and hardware vulnerabilities in the form of hardware Trojans may alter control signals to disrupt the circuit's control flow and introduce unconventional delays in the critical hardware of PQC. Hardware Trojans, especially on control signals, are more low cost and impactful than data signals because a single corrupted control signal can disrupt or bypass entire computation sequences, whereas data faults usually cause only localized errors. On the other hand, adversaries can perform Soft Analytical Side Channel Attacks (SASCA) on the design using the inserted hardware Trojan. In this paper, we present a secure NTT architecture capable of detecting unconventional delays, control-flow disruptions, and SASCA, while providing an adaptive fault-correction methodology for their mitigation. Extensive simulations and implementations of our Secure NTT on Artix-7 FPGA with different Kyber variants show that our fault detection and correction modules can efficiently detect and correct faults whether caused unintentionally or intentionally by hardware Trojans with a high success rate, while introducing only modest area and time overheads.

翻译：数论变换（NTT）是基于格的后量子密码（PQC）算法（如Kyber、Dilithium、NTRU等）中多项式乘法最核心的组件。然而，以硬件特洛伊木马形式出现的侧信道攻击（SCA）和硬件漏洞可能篡改控制信号，破坏电路的控制流，并在PQC关键硬件中引入非传统延迟。硬件特洛伊木马（尤其是作用于控制信号的）比数据信号更隐蔽且更具破坏性，因为单个被篡改的控制信号就能破坏或绕过整个计算序列，而数据故障通常仅造成局部错误。另一方面，攻击者可以利用插入的硬件特洛伊木马对设计进行软分析侧信道攻击（SASCA）。本文提出一种安全的NTT架构，能够检测非传统延迟、控制流中断以及SASCA，并提供一种自适应故障纠正方法以缓解这些威胁。我们在Artix-7 FPGA上使用不同Kyber变体对安全NTT进行了大量仿真与实现，结果表明：无论故障由无意引发或由硬件特洛伊木马蓄意造成，我们的故障检测与纠正模块均能以高成功率进行有效检测和纠正，同时仅引入适度的面积与时间开销。