Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their strong programming capabilities. However, no work has yet considered using LLMs for bug localization in Verilog code. This paper presents Location-is-Key, an opensource LLM solution to locate functional errors in Verilog snippets. LiK achieves high localization accuracy, with a pass@1 localization accuracy of 93.3% on our test dataset based on RTLLM, surpassing GPT-4's 77.9% and comparable to Claude-3.5's 90.8%. Additionally, the bug location obtained by LiK significantly improves GPT-3.5's bug repair efficiency (Functional pass@1 increased from 40.39% to 58.92%), highlighting the importance of bug localization in LLM-based Verilog debugging. Compared to existing methods, LiK only requires the design specification and the erroneous code snippet, without the need for testbenches, assertions, or any other EDA tools. This research demonstrates the feasibility of using LLMs for Verilog error localization, thus providing a new direction for automatic Verilog code debugging.

翻译：Verilog代码中的错误定位是硬件设计验证过程中至关重要且耗时的工作。自问世以来，大型语言模型（LLMs）已展现出强大的编程能力。然而，目前尚未有研究探索利用LLMs进行Verilog代码的错误定位。本文提出Location-is-Key（LiK）——一个开源的LLM解决方案，用于定位Verilog代码片段中的功能错误。LiK实现了高精度的定位能力，在我们基于RTLLM构建的测试数据集上达到93.3%的pass@1定位准确率，超越GPT-4的77.9%，并与Claude-3.5的90.8%表现相当。此外，LiK提供的错误定位结果显著提升了GPT-3.5的错误修复效率（功能pass@1率从40.39%提升至58.92%），凸显了错误定位在基于LLM的Verilog调试中的重要性。相较于现有方法，LiK仅需设计规范和错误代码片段，无需测试平台、断言或任何其他EDA工具。本研究证明了利用LLMs进行Verilog错误定位的可行性，从而为自动化Verilog代码调试提供了新的研究方向。