Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the potential to significantly reduce or eliminate costly data movement between processing elements and main memory. Prior works experimentally demonstrate three-input MAJ (i.e., MAJ3) and two-input AND and OR operations in commercial off-the-shelf (COTS) DRAM chips. Yet, demonstrations on COTS DRAM chips do not provide a functionally complete set of operations (e.g., NAND or AND and NOT). We experimentally demonstrate that COTS DRAM chips are capable of performing 1) functionally-complete Boolean operations: NOT, NAND, and NOR and 2) many-input (i.e., more than two-input) AND and OR operations. We present an extensive characterization of new bulk bitwise operations in 256 off-the-shelf modern DDR4 DRAM chips. We evaluate the reliability of these operations using a metric called success rate: the fraction of correctly performed bitwise operations. Among our 19 new observations, we highlight four major results. First, we can perform the NOT operation on COTS DRAM chips with a 98.37% success rate on average. Second, we can perform up to 16-input NAND, NOR, AND, and OR operations on COTS DRAM chips with high reliability (e.g., 16-input NAND, NOR, AND, and OR with an average success rate of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). Third, data pattern only slightly affects bitwise operations. Our results show that executing NAND, NOR, AND, and OR operations with random data patterns decreases the success rate compared to all logic-1/logic-0 patterns by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. Fourth, bitwise operations are highly resilient to temperature changes, with small success rate fluctuations of at most 1.66% among all the tested operations when the temperature is increased from 50C to 95C.

翻译：利用DRAM计算（Processing-using-DRAM, PuD）是一种新兴范式，通过利用DRAM电路的模拟运算特性实现大规模并行内存计算。该技术有望大幅减少甚至消除处理单元与主存之间代价高昂的数据搬运。先前研究已在商用现货（COTS）DRAM芯片上实验验证了三输入多数门（即MAJ3）以及二输入与门和或门操作。然而，COTS DRAM芯片上的验证尚未提供功能完备的操作集（如与非门、与门和非门）。我们通过实验证明，COTS DRAM芯片能够执行：（1）功能完备的布尔运算：非门、与非门和或非门；（2）多输入（即超过两输入）的与门和或门操作。我们对256个现成现代DDR4 DRAM芯片中的新型大规模位运算进行了全面表征。采用称为"成功率"（正确执行位运算的比例）的指标评估这些操作的可靠性。在19项新发现中，我们重点提出四项主要结论：第一，在COTS DRAM芯片上执行非门操作的平均成功率达98.37%；第二，可高可靠性地执行最多16输入的与非门、或非门、与门和或门操作（例如16输入与非门、或非门、与门和或门的平均成功率分别为94.94%、95.87%、94.94%和95.85%）；第三，数据模式对位运算影响较小。实验表明，相较于全逻辑1/逻辑0模式，随机数据模式执行与非门、或非门、与门和或门操作时成功率分别下降1.39%、1.97%、1.43%和1.98%；第四，位运算对温度变化具有高度鲁棒性，当温度从50℃升至95℃时，所有测试操作的成功率波动幅度不超过1.66%。