The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating hardware description and design. LLMs, known for generating human-like content, are now being explored for creating hardware description languages (HDLs) like Verilog from natural language inputs. This approach aims to enhance productivity and reduce costs in VLSI system design. The study introduces "AiEDA", a proposed agentic design flow framework for digital ASIC systems, leveraging autonomous AI agents to manage complex design tasks. AiEDA is designed to streamline the transition from conceptual design to GDSII layout using an open-source toolchain. The framework is demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting (KWS). The use of agentic AI workflows promises to improve design efficiency by automating the integration of multiple design tools, thereby accelerating the development process and addressing the complexities of hardware design.

翻译：本文探讨了生成式人工智能（GenAI）与数字芯片设计领域的最新进展，重点研究了大型语言模型（LLMs）在硬件描述与设计自动化中的集成应用。LLMs以其生成类人内容的能力而闻名，目前正被探索用于从自然语言输入生成硬件描述语言（HDL，如Verilog）。该方法旨在提升超大规模集成电路（VLSI）系统设计的生产力并降低成本。本研究提出了“AiEDA”——一种面向数字专用集成电路（ASIC）系统的智能体设计流程框架，该框架利用自主AI智能体来管理复杂的设计任务。AiEDA旨在通过开源工具链，实现从概念设计到GDSII版图的流畅转换。本文通过设计一款用于关键词检测（KWS）的超低功耗数字ASIC，对该框架进行了验证。采用智能体AI工作流有望通过自动化集成多种设计工具来提升设计效率，从而加速开发进程并应对硬件设计的复杂性。