The adoption of high-performance multi-core platforms in avionics and automotive systems introduces significant challenges in ensuring predictable execution, primarily due to shared resource interferences. Many existing approaches study interference from a single angle-for example, through hardware-level analysis or by monitoring software execution. However, no single abstraction level is sufficient on its own. Hardware behavior, program structure, and system configuration all interact, and a complete view is needed to understand where interferences come from and how to reduce them. In this paper, we present a methodology that brings together several tools that operate at different abstraction levels. At the lowest level, PHYLOG provides a formal model of the hardware and identifies possible interference channels using micro-architectural transactions. At the program level, machine learning analysis locates the exact parts of the code that are most sensitive to shared-resource contention. At the compilation level, MLIR-based transformations use this information to reshape memory access patterns and reduce pressure on shared resources. Finally, at the system level, Linux cgroups enforce static execution constraints to prevent highly interfering tasks from running together. The goal of our approach is to reduce memory interference and improve the system's predictability, thereby easing the certification process of multi-core systems in safety-critical domains.

翻译：在航空电子和汽车系统中采用高性能多核平台带来了确保可预测执行方面的重大挑战，这主要是由于共享资源干扰所致。许多现有方法仅从单一角度研究干扰——例如通过硬件级分析或监控软件执行。然而，没有任何单一抽象层级能够独立胜任。硬件行为、程序结构和系统配置相互影响，需要全面视角才能理解干扰的来源及缓解方法。本文提出一种整合了多个不同抽象层级工具的方法论：在最底层，PHYLOG提供硬件形式化模型，并通过微架构事务识别可能的干扰通道；在程序层级，机器学习分析精确定位代码中对共享资源争用最敏感的部分；在编译层级，基于MLIR的转换利用这些信息重塑内存访问模式，减少对共享资源的压力；最后在系统层级，Linux cgroups实施静态执行约束，防止高干扰任务同时运行。本方法旨在减少内存干扰，提升系统可预测性，从而简化安全关键领域多核系统的认证流程。