Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. This paper describes Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibility and hardware efficiency of Register-Transfer Level (RTL) design. The language's concise syntax, matched with a hardware design-friendly execution model, permits a relatively simple toolchain to map high-level code into efficient hardware implementations.

翻译：数字系统的重要性日益凸显，计算硬件的异构性不断增强。然而，硬件设计过程依然耗时且成本高昂，部分原因在于传统硬件描述语言（如VHDL和Verilog）的局限性。长期以来，研究界一直致力于实现像软件一样编程硬件，即通过高级语言生成高效的硬件设计。本文提出Kanagawa语言，该语言采用全新方法，将传统高层次综合（HLS）方法的编程效率优势与寄存器传输级（RTL）设计的表达能力和硬件效率相结合。该语言具有简洁的语法，并匹配硬件设计友好的执行模型，使得相对简单的工具链能够将高级代码映射为高效的硬件实现。