High-speed switch packet scheduling demands both line-rate performance and programmability. Existing programmable hardware scheduling models, such as PIFO and PIEO, can express a broad range of scheduling algorithms; however, their semantics are restricted to packet-level ordering and cannot dynamically reorder buffered packets, which limits the support for dynamic-ordering algorithms such as pFabric. To overcome this limitation, we propose UIFO (Update-In-First-Out), a new programmable scheduling model that introduces a two-level abstraction over classes and packets. UIFO enables dynamic updates to the scheduling order at the class level while preserving in-order packet scheduling within each class, thereby supporting dynamic reordering of already-buffered packets. Furthermore, UIFO remains fully compatible with and generalizes existing PIFO and PIEO models. We implement a hardware prototype of UIFO based on priority-queue designs and evaluate it on an FPGA platform and in a 28 nm ASIC process. Overall, UIFO significantly enhances scheduling expressiveness and maintains favorable scalability while sustaining 100 Gbps line-rate throughput.

翻译：高速交换机数据包调度要求同时具备线速性能和可编程性。现有可编程硬件调度模型（如PIFO和PIEO）可表达广泛的调度算法，但其语义局限于数据包级别排序，无法对已缓冲数据包进行动态重排序，这限制了对pFabric等动态排序算法的支持。为克服这一局限，我们提出UIFO（Update-In-First-Out）这一新型可编程调度模型，该模型引入类别与数据包的两级抽象。UIFO支持在类别级别动态更新调度顺序，同时保持每个类别内的数据包顺序调度，从而实现对已缓冲数据包的动态重排序。此外，UIFO完全兼容并泛化了现有PIFO和PIEO模型。我们基于优先级队列设计实现了UIFO硬件原型，并在FPGA平台和28纳米ASIC工艺上进行了评估。总体而言，UIFO显著增强了调度表达能力，在保持良好可扩展性的同时，可维持100 Gbps线速吞吐率。