In recent years, there has been an exponential growth in the size and complexity of System-on-Chip designs targeting different specialized applications. The cost of an undetected bug in these systems is much higher than in traditional processor systems as it may imply the loss of property or life. The problem is further exacerbated by the ever-shrinking time-to-market and ever-increasing demand to churn out billions of devices. Despite decades of research in simulation and formal methods for debugging and verification, it is still one of the most time-consuming and resource intensive processes in contemporary hardware design cycle. In this work, we propose VeriBug, which leverages recent advances in deep learning to accelerate debugging at the Register-Transfer Level and generates explanations of likely root causes. First, VeriBug uses control-data flow graph of a hardware design and learns to execute design statements by analyzing the context of operands and their assignments. Then, it assigns an importance score to each operand in a design statement and uses that score for generating explanations for failures. Finally, VeriBug produces a heatmap highlighting potential buggy source code portions. Our experiments show that VeriBug can achieve an average bug localization coverage of 82.5% on open-source designs and different types of injected bugs.

翻译：近年来，面向不同专业应用的片上系统设计在规模和复杂性上呈指数级增长。与传统的处理器系统相比，这类系统中未被发现的缺陷可能造成财产甚至生命损失，因此代价更为高昂。不断缩短的产品上市周期与持续增长的数十亿级设备出货需求，进一步加剧了该问题的严峻性。尽管在调试和验证领域的仿真与形式化方法已历经数十年研究，但这些过程仍是当代硬件设计周期中最耗时、最耗费资源的环节之一。本文提出的VeriBug框架，利用深度学习的最新进展加速寄存器传输级调试，并生成可能根本原因的解释。首先，VeriBug通过分析操作数及其赋值的上下文，学习硬件设计的控制数据流图并执行设计语句；其次，它为设计语句中的每个操作数分配重要性分数，并以此生成故障解释；最后，VeriBug生成热力图，突出显示可能存在缺陷的源代码区域。实验表明，在开源设计及不同类型的注入缺陷测试中，VeriBug的平均缺陷定位覆盖率可达82.5%。