Noisy intermediate-scale quantum (NISQ) processors are entering an early fault-tolerance regime where full quantum error correction carries prohibitive resource costs, yet lightweight error detection can meaningfully improve algorithmic success rates. Existing compilation and error-detection toolchains treat these concerns in isolation, with no principled way to balance detection overhead against success probability under latency constraints. We present an integrated hardware-aware compilation and data-driven quantum error-detection (QED) framework that jointly optimises qubit mapping, SWAP insertion, and syndrome-schedule placement via a noise-weighted cost function and a learned multi-objective scheduler. Simulation experiments on an HPC cluster using GPU-accelerated density-matrix simulation (NVIDIA cuQuantum SDK) across VQE, phase-estimation, and Grover benchmarks, three noise profiles, and circuit sizes of 6-20 qubits (depths 10-160), show that joint co-design raises algorithmic success probability by up to 68 percent (95 percent CI: 60 percent to 76 percent) over SABRE on an 8-qubit VQE instance with post-selection.

翻译：含噪中等规模量子（NISQ）处理器正进入早期容错阶段，此时全量子纠错所需资源成本高昂，而轻量级错误检测能显著提升算法成功率。现有编译与错误检测工具链将两者孤立处理，缺乏在延迟约束下平衡检测开销与成功概率的规范化方法。我们提出一种集成的硬件感知编译与数据驱动量子错误检测（QED）框架，通过噪声加权代价函数与学习型多目标调度器，联合优化量子比特映射、SWAP插入与综合征调度方案。基于HPC集群的GPU加速密度矩阵仿真（NVIDIA cuQuantum SDK）实验，涵盖VQE、相位估计与Grover基准测试、三种噪声模型以及6-20量子比特（深度10-160）电路规模，结果表明：在8量子比特VQE实例上采用后选择时，联合协同设计相比SABRE将算法成功概率提升高达68%（95%置信区间：60%至76%）。