When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. Gate clustering is even more important for netlist partitioning targeting 3D system integration. In this paper, we make the argument that the choice of clustering method for 3D-ICs partitioning is not trivial and deserves careful consideration. To support our claim, we implemented three clustering methods that were used prior to partitioning two synthetic designs representing two extremes of the circuits medium/long interconnect diversity spectrum. Automatically partitioned netlists are then placed and routed in 3D to compare the impact of clustering methods on several metrics. From our experiments, we see that the clustering method indeed has a different impact depending on the design considered and that a circuit-blind, universal partitioning method is not the way to go, with wire-length savings of up to 31%, total power of up to 22%, and effective frequency of up to 15% compared to other methods. Furthermore, we highlight that 3D-ICs open new opportunities to design systems with a denser interconnect, drastically reducing the design utilization of circuits that would not be considered viable in 2D.

翻译：在基于图的门级网表划分中，通过聚类降低图的阶数并保留划分可能退化的电路特性具有显著优势。针对三维系统集成的网表划分，门级聚类尤为重要。本文论证三维集成电路划分中聚类方法的选择并非琐事，需要审慎考量。为支撑这一论断，我们实现了三种聚类方法，用于对代表电路中等/长互连多样性谱系两极的两个合成设计进行预划分。随后对自动划分的网表进行三维布局布线，以比较聚类方法对多项指标的影响。实验表明，聚类方法确实因设计而异，盲目的通用划分方法不可取——与其它方法相比，该方法可实现最高31%的线长节省、22%的总功耗降低及15%的有效频率提升。此外，我们强调三维集成电路为设计更高密度的互连系统开辟了新机遇，可大幅降低在二维设计中不可行的电路设计利用率。