Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components. First, a PTW cost predictor (PTW-CP) identifies costly-to-translate addresses based on the frequency and cost of the PTWs they lead to. Second, a TLB-aware cache replacement policy prioritizes keeping TLB entries in the cache hierarchy by considering (i) the translation pressure (e.g., last-level TLB miss rate) and (ii) the reuse characteristics of the TLB entries. Our evaluation results show that in native (virtualized) execution environments Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design and by 6.2% (20.1%) over a state-of-the-art software-managed TLB, across 11 diverse data-intensive workloads. Victima (i) is effective in both native and virtualized environments, (ii) is completely transparent to application and system software, and (iii) incurs very small area and power overheads on a modern high-end CPU.

翻译：地址翻译是数据密集型工作负载的性能瓶颈，原因在于大尺寸数据集和不规则访存模式导致频繁发生高延迟页表遍历（PTW）。当前减少PTW的方法包括：（i）大型硬件TLB或（ii）大型软件管理TLB。然而，这两种方案均存在显著缺陷：增大访问延迟、功耗与面积开销（硬件TLB方案），以及昂贵的内存访问、大块连续内存需求与复杂的操作系统修改（软件管理TLB方案）。我们提出Victima——一种新型软件透明机制，通过利用缓存层级中未充分利用的资源大幅提升处理器地址翻译覆盖范围。其核心思想是将L2缓存块重新用于存储TLB条目簇，从而提供支持末级TLB的低延迟大容量备份组件，进而减少PTW。Victima包含两个主要组件：第一，PTW代价预测器（PTW-CP）基于所引发PTW的频率与代价识别高成本翻译地址；第二，TLB感知缓存替换策略通过综合考虑（i）翻译压力（如末级TLB缺失率）与（ii）TLB条目的重用特征，优先在缓存层级中保留TLB条目。评估结果表明，在原生（虚拟化）执行环境下，相较于基于四级基数树的页表设计基线，Victima在11种多样化数据密集型负载上平均提升应用端到端性能7.4%（28.7%）；相较于先进软件管理TLB方案提升6.2%（20.1%）。Victima（i）在原生与虚拟化环境中均有效，（ii）对应用与系统软件完全透明，（iii）在现代高端CPU上仅产生极小的面积与功耗开销。