Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handling of incoming events. However, RISC- V processors are still lagging in this area compared to more mature proprietary architectures, such as ARM Cortex-M and TriCore, which have been tuned for years. The default interrupt controller standardized by RISC-V, the Core Local Interruptor (CLINT), lacks configurability in prioritization and preemption of interrupts. The RISC-V Core Local Interrupt Controller (CLIC) specification addresses this concern by enabling pre-emptible, low-latency vectored interrupts while also envisioning optional extensions to improve interrupt latency. In this work, we implement a CLIC for the CV32E40P, an industrially supported open-source 32-bit MCU-class RISC-V core, and enhance it with fastirq: a custom extension that provides interrupt latency as low as 6 cycles. We call CV32RT our enhanced core. To the best of our knowledge, CV32RT is the first fully open-source RV32 core with competitive interrupt-handling features compared to the Arm Cortex-M series and TriCore. The proposed extensions are also demonstrated to improve task context switching in real-time operating systems.

翻译：采用开源RISC-V指令集的处理器在嵌入式领域的应用日益广泛。众多嵌入式场景具有实时性约束，要求对事件响应具备灵活性、可预测性及快速反应能力。然而，相较于ARM Cortex-M与TriCore等经多年优化的成熟专有架构，RISC-V处理器在此领域仍显滞后。RISC-V标准化的默认中断控制器——核本地中断器（CLINT）缺乏对中断优先级及抢占的可配置性。RISC-V核本地中断控制器（CLIC）规范通过支持可抢占的低延迟向量中断，并规划可选的扩展机制以降低中断延迟，从而解决了上述问题。本研究为工业级开源32位MCU级RISC-V核CV32E40P实现了CLIC，并通过自定义扩展fastirq对其增强，使中断延迟低至6个时钟周期。我们将增强后的内核命名为CV32RT。据我们所知，CV32RT是首个具备与Arm Cortex-M系列及TriCore竞争性中断处理特性的全开源RV32内核。实验证明，所提出的扩展机制还能有效改善实时操作系统中的任务上下文切换性能。