High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant's thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.

翻译：摘要：高性能计算（HPC）处理器是当今集成的信息物理系统，需要复杂且高带宽的闭环功率与热控制策略。为高效满足实时多输入多输出（MIMO）最优功率需求，高端处理器集成了片上功率控制器系统（PCS）。传统PCS基于简单的微控制器（MCU）级核心，但为支持管理不断增加的核数、功率状态以及工艺、电压和温度变化带来的先进MIMO控制算法，需要更具可扩展性和灵活性的PCS架构。本文提出ControlPULP——一个开源、软硬件协同的RISC-V并行PCS平台，其由具备快速中断处理的单核MCU、可扩展的多核可编程集群加速器以及专用DMA引擎组成，用于实时功率管理策略的并行加速。ControlPULP依赖FreeRTOS调度反应式功率控制固件（PCF）应用层。我们在面向下一代72核HPC处理器的功率管理用例中验证了ControlPULP。首先，多核集群加速了PCF，相比单核执行实现4.9倍加速，且可在控制超周期内以极低面积开销（约占现代HPC CPU芯片面积的0.1%）支持更先进的功率管理算法。随后，通过设计基于FPGA的闭环仿真框架（利用异构SoC范式），对PCS和PCF进行评估：与等效软件模型在环方法相比，该框架的DVFS跟踪平均偏差在处理器热设计功耗（TDP）的3%以内。最后，在计算密集型工作负载下，所提PCF的性能优于工业级控制算法。