Dynamic Random Access Memory (DRAM) is pervasive in computer systems. Cell vulnerabilities caused by unintended phenomena (forced retention failure, latency alteration, rowhammer and rowpress) lead to unintended bit flips in memory. These phenomena have been explored as attacks to violate data integrity and confidentiality during normal operation, but also exploited as a benefit in security systems as a method to generate random secret keys and unique device fingerprints (e.g. Physically Unclonable Functions). In both cases, attackers may wish to exploit knowledge of individual cell flip vulnerability to predict the current/future data contents of a set of cells, which can be utilised to break security systems. In this work, we develop a quantitative, cell-level circuit framework that models DRAM vulnerability directly from its physical charge leakage and disturbance pathways. By linking these device-layer behaviours to system-level security properties, our framework enables systematic evaluation of DRAM with respect to volatility (retention), integrity (disturbance-induced modification), and confidentiality (pattern-dependent leakage). We further demonstrate how the framework can be applied to well-known failure modes, revealing non-uniform and context-dependent vulnerability patterns. This work provides both theoretical foundations and practical evaluation tools for evaluating the suitability of DRAM use within security applications.

翻译：动态随机存取存储器（DRAM）在计算机系统中无处不在。由非预期现象（强制保持失效、延迟改变、行锤攻击和行挤压）引发的单元漏洞会导致存储器中出现非预期的比特翻转。这些现象已被探索为攻击手段，可破坏正常运行期间数据的完整性与机密性，同时也被利用为安全系统中的优势方法，用于生成随机密钥和独有设备指纹（如物理不可克隆函数）。在这两种场景下，攻击者可能希望利用对单个单元翻转漏洞的知识，预测一组单元当前或未来的数据内容，进而用于破解安全系统。本研究开发了一种定量化的单元级电路框架，该框架直接从DRAM的物理电荷泄漏和干扰路径出发，对其漏洞进行建模。通过将这些器件层行为与系统级安全属性相关联，我们的框架能够系统性地评估DRAM在易失性（保持特性）、完整性（干扰诱导的修改）和机密性（模式依赖的泄漏）方面的表现。我们进一步展示了该框架如何应用于已知的失效模式，揭示了非均匀且依赖上下文的漏洞模式。这项工作为评估DRAM在安全应用中的适用性提供了理论基础和实用评估工具。