Multi-die FPGAs are crucial components in modern computing systems, particularly for high-performance applications such as artificial intelligence and data centers. Super long lines (SLLs) provide interconnections between super logic regions (SLRs) for a multi-die FPGA on a silicon interposer. They have significantly higher delay compared to regular interconnects, which need to be minimized. With the increase in design complexity, the growth of SLLs gives rise to challenges in timing and power closure. Existing placement algorithms focus on optimizing the number of SLLs but often face limitations due to specific topologies of SLRs. Furthermore, they fall short of achieving continuous optimization of SLLs throughout the entire placement process. This highlights the necessity for more advanced and adaptable solutions. In this paper, we propose LEAPS, a comprehensive, systematic, and adaptable multi-die FPGA placement algorithm for SLL minimization. Our contributions are threefold: 1) proposing a high-performance global placement algorithm for multi-die FPGAs that optimizes the number of SLLs while addressing other essential design constraints such as wirelength, routability, and clock routing; 2) introducing a versatile method for more complex SLR topologies of multi-die FPGAs, surpassing the limitations of existing approaches; and 3) executing continuous optimization of SLLs across the whole placement stages, including global placement (GP), legalization (LG), and detailed placement (DP). Experimental results demonstrate the effectiveness of LEAPS in reducing SLLs and enhancing circuit performance. Compared with the most recent state-of-the-art (SOTA) method, LEAPS achieves an average reduction of 43.08% in SLLs and 9.99% in HPWL, while exhibiting a notable 34.34$\times$ improvement in runtime.

翻译：多芯片FPGA是现代计算系统的关键组件，尤其适用于人工智能和数据中心等高性能应用。超长连线（SLLs）用于在硅中介层上的多芯片FPGA的超逻辑区域（SLRs）之间提供互连。与常规互连相比，SLLs具有显著更高的延迟，需要予以最小化。随着设计复杂度的增加，SLLs的增长给时序和功耗收敛带来了挑战。现有布局算法侧重于优化SLL数量，但常受限于SLR的特定拓扑结构。此外，这些算法无法在整个布局过程中实现对SLLs的持续优化。这凸显了对更先进、更灵活解决方案的需求。本文提出LEAPS——一种全面、系统且自适应的多芯片FPGA布局算法，用于最小化SLLs。我们的贡献包括三方面：1）提出针对多芯片FPGA的高性能全局布局算法，在优化SLL数量的同时处理线长、可布线性和时钟布线等其他关键设计约束；2）引入一种通用方法，以应对多芯片FPGA中更复杂的SLR拓扑结构，突破现有方法的局限性；3）在整个布局阶段（包括全局布局（GP）、合法化（LG）和详细布局（DP））持续优化SLLs。实验结果表明，LEAPS在减少SLLs和提升电路性能方面具有有效性。与最新最先进（SOTA）方法相比，LEAPS平均减少43.08%的SLLs和9.99%的HPWL，同时运行时间提升34.34倍。