Integrated circuit verification has gathered considerable interest in recent times. Since these circuits keep growing in complexity year by year, pre-Silicon (pre-SI) verification becomes ever more important, in order to ensure proper functionality. Thus, in order to reduce the time needed for manually verifying ICs, we propose a machine learning (ML) approach, which uses less simulations. This method relies on an initial evaluation set of operating condition configurations (OCCs), in order to train Gaussian process (GP) surrogate models. By using surrogate models, we can propose further, more difficult OCCs. Repeating this procedure for several iterations has shown better GP estimation of the circuit's responses, on both synthetic and real circuits, resulting in a better chance of finding the worst case, or even failures, for certain circuit responses. Thus, we show that the proposed approach is able to provide OCCs closer to the specifications for all circuits and identify a failure (specification violation) for one of the responses of a real circuit.

翻译：集成电路验证近年来引起了广泛关注。由于这些电路的复杂性逐年增加，硅前（pre-SI）验证在确保功能正确性方面变得愈发重要。因此，为了减少手动验证集成电路所需的时间，我们提出了一种机器学习（ML）方法，该方法使用较少的仿真次数。该方法依赖于一组初始的运行条件配置（OCC）来训练高斯过程（GP）代理模型。通过使用代理模型，我们可以提出更具挑战性的OCC。重复这一过程多次后，在合成电路和实际电路上，GP对电路响应的估计效果均有所提升，从而更有可能发现最坏情况，甚至检测到某些电路响应的失效。因此，我们证明所提出的方法能够为所有电路提供更接近规格的OCC，并识别出一个实际电路中某一响应的失效（规格违反）。