This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performance. Incorporating FPGA-based GNNs into particle detectors presents a unique challenge since it requires sub-microsecond latency to deploy the networks for online event selection with a data rate of hundreds of terabytes per second in the Level-1 triggers at the CERN Large Hadron Collider experiments. This paper proposes a novel outer-product based matrix multiplication approach, which is enhanced by exploiting the structured adjacency matrix and a column-major data layout. Moreover, a fusion step is introduced to further reduce the end-to-end design latency by eliminating unnecessary boundaries. Furthermore, a GNN-specific algorithm-hardware co-design approach is presented which not only finds a design with a much better latency but also finds a high accuracy design under given latency constraints. To facilitate this, a customizable template for this low latency GNN hardware architecture has been designed and open-sourced, which enables the generation of low-latency FPGA designs with efficient resource utilization using a high-level synthesis tool. Evaluation results show that our FPGA implementation is up to 9.0 times faster and consumes up to 12.4 times less power than a GPU implementation. Compared to the previous FPGA implementations, this work achieves 6.51 to 16.7 times lower latency. Moreover, the latency of our FPGA design is sufficiently low to enable deployment of GNNs in a sub-microsecond, real-time collider trigger system, enabling it to benefit from improved accuracy. The proposed LL-GNN design advances the next generation of trigger systems by enabling sophisticated algorithms to process experimental data efficiently.

翻译：本文提出一种用于粒子探测器的低延迟图神经网络（LL-GNN）可重构架构，实现了前所未有的低延迟性能。将基于FPGA的GNN集成到粒子探测器中面临独特挑战，因为需要在CERN大型强子对撞机实验的一级触发器中，以每秒数百太字节的数据速率部署网络进行在线事件选择，且延迟需低于微秒级。本文提出了一种基于外积的新型矩阵乘法方法，通过利用结构化邻接矩阵和列优先数据布局进行增强。此外，引入融合步骤来消除不必要的边界，进一步降低端到端设计延迟。同时，提出了一种GNN专用的算法-硬件协同设计方法，不仅能找到延迟显著更优的设计，还能在给定延迟约束下找到高精度设计。为便于实现，我们设计并开源了该低延迟GNN硬件架构的可定制模板，利用高层次综合工具即可生成资源高效的FPGA低延迟设计。评估结果表明，我们的FPGA实现比GPU实现快9.0倍，功耗降低12.4倍。与之前的FPGA实现相比，本工作延迟降低6.51至16.7倍。此外，FPGA设计的延迟足够低，足以在亚微秒级实时对撞机触发系统中部署GNN，从而受益于更高的精度。所提出的LL-GNN设计通过使复杂算法高效处理实验数据，推动了下一代触发系统的发展。