As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automated design environment that explores LLMs to generate hardware logic designs from natural language specifications. To realize a more accessible and efficient chip development flow, we present a scalable four-stage zero-code logic design framework based on LLMs without retraining or finetuning. At first, the demo, ChipGPT, begins by generating prompts for the LLM, which then produces initial Verilog programs. Second, an output manager corrects and optimizes these programs before collecting them into the final design space. Eventually, ChipGPT will search through this space to select the optimal design under the target metrics. The evaluation sheds some light on whether LLMs can generate correct and complete hardware logic designs described by natural language for some specifications. It is shown that ChipGPT improves programmability, and controllability, and shows broader design optimization space compared to prior work and native LLMs alone.

翻译：随着ChatGPT等大型语言模型展现出前所未有的机器智能，它们在协助硬件工程师通过自然语言交互实现更高效逻辑设计方面也表现出色。为评估大型语言模型辅助硬件设计过程的潜力，本文尝试构建一个自动化设计环境，探索利用大型语言模型从自然语言规范生成硬件逻辑设计。为实现更易用、更高效的芯片开发流程，我们提出一种基于大型语言模型的可扩展四阶段无代码逻辑设计框架，无需重新训练或微调。首先，演示系统ChipGPT通过为大型语言模型生成提示词，使其输出初始Verilog程序；其次，输出管理器对这些程序进行修正与优化，并将其纳入最终设计空间；最后，ChipGPT在该空间中搜索，以在目标指标下选择最优设计。评估结果揭示了大型语言模型能否为某些规范生成由自然语言描述的正确且完整的硬件逻辑设计。研究表明，与先前工作及原生大型语言模型相比，ChipGPT提升了可编程性与可控性，并展现出更广泛的设计优化空间。