Many-hypercube codes, concatenated ${[[n,n-2,2]]}$ quantum error-detecting codes ($n$ is even), have recently been proposed as high-rate quantum codes suitable for fault-tolerant quantum computing. While the original many-hypercube codes with ${n=6}$ can achieve remarkably high encoding rates (about 30% and 20% at concatenation levels 3 and 4, respectively), they have large code block sizes at high levels (216 and 1296 physical qubits per block at levels 3 and 4, respectively), making not only experimental realization difficult but also logical error rates per code block high. Toward earlier experimental realization and lower logical error rates, here we comprehensively investigate smaller many-hypercube codes with $[[6,4,2]]$ and/or $[[4,2,2]]$ codes, where, e.g., $D_{6,4,4}$ denotes the many-hypercube code using $[[6,4,2]]$ at level 1 and $[[4,2,2]]$ at levels 2 and 3. As a result, we found a counterintuitive fact that $D_{6,4,4}$ ($D_{6,6,4,4}$) can achieve lower logical error rates per code block than $D_{4,4,4}$ ($D_{4,4,4,4}$), despite its higher encoding rate and larger code block size. Focusing on level 3, we also developed efficient fault-tolerant encoders realizing about 60% overhead reduction while maintaining or even improving the performance, compared to the original design. Using them, we numerically confirmed that $D_{6,4,4}$ also achieves the best performance for logical controlled-NOT gates in a circuit-level noise model. These results are important for targeting a high-rate code toward early experimental realization of efficient fault-tolerant quantum computing.

翻译：多超立方体码——一种由${[[n,n-2,2]]}$量子检错码（$n$为偶数）级联构成的编码方案——近期被提出作为适用于容错量子计算的高码率量子码。虽然原始采用${n=6}$的多超立方体码能够实现极高的编码率（在3级和4级级联时分别达到约30%和20%），但其在高层级具有较大的码块规模（在3级和4级时每个码块分别需要216和1296个物理量子比特），这不仅使得实验实现困难，也导致每个码块的逻辑错误率较高。为了推动更早的实验实现与更低的逻辑错误率，本文系统研究了采用$[[6,4,2]]$和/或$[[4,2,2]]$码构建的更小型多超立方体码，其中例如$D_{6,4,4}$表示在第1级使用$[[6,4,2]]$码、在第2和第3级使用$[[4,2,2]]$码的多超立方体码。结果我们发现了一个反直觉的事实：尽管$D_{6,4,4}$（及$D_{6,6,4,4}$）具有更高的编码率和更大的码块规模，但其每个码块的逻辑错误率可以低于$D_{4,4,4}$（及$D_{4,4,4,4}$）。针对3级级联情形，我们还开发了高效的容错编码器，相较于原始设计，在保持甚至提升性能的同时实现了约60%的开销降低。基于这些编码器，我们通过数值模拟证实，在电路级噪声模型下，$D_{6,4,4}$在逻辑受控非门操作中也实现了最佳性能。这些结果对于推动高码率编码方案走向高效容错量子计算的早期实验实现具有重要意义。