Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing multi-level logic optimization algorithms often employ greedy approaches with a series of local optimization steps. Each step breaks the circuit into small pieces (e.g., k-feasible cuts) and applies incremental changes to individual pieces separately. These local optimization steps could limit the exploration space and may miss opportunities for significant improvements. To address the limitation, this paper proposes using e-graph in logic synthesis. The new workflow, named Esyn, makes use of the well-established e-graph infrastructure to efficiently perform logic rewriting. It explores a diverse set of equivalent Boolean representations while allowing technology-aware cost functions to better support delay-oriented and area-oriented logic synthesis. Experiments over a wide range of benchmark designs show our proposed logic optimization approach reaches a wider design space compared to the commonly used AIG-based logic synthesis flow. It achieves on average 15.29% delay saving in delay-oriented synthesis and 6.42% area saving for area-oriented synthesis.

翻译：逻辑综合在数字设计流程中扮演着关键角色，对电路实现的最终结果质量（QoR）具有决定性影响。然而，现有的多层逻辑优化算法通常采用贪心方法，通过一系列局部优化步骤实现。每个步骤将电路分解为小单元（如k-可行割集），并分别对各个单元进行增量式修改。这种局部优化步骤可能限制探索空间，并错失显著改进的机会。为弥补这一局限，本文提出在逻辑综合中使用E图（e-graph）。该新工作流命名为Esyn，利用成熟的E图基础设施高效执行逻辑重写，在探索多种等价布尔表示的同时，允许采用技术感知代价函数更好地支持面向延迟和面向面积的逻辑综合。在大量基准设计上的实验表明，与常用的基于AIG的逻辑综合流程相比，我们提出的逻辑优化方法达到了更广泛的设计空间，在面向延迟的综合中平均实现15.29%的延迟节省，在面向面积的综合中实现6.42%的面积节省。