The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether inherent or stemming from soft errors, can result in gate malfunction, ultimately can cause gates to malfunction, which in turn results in incorrect multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ a reliable finite field multiplier implementation that boasts a robust fault detection capability. In order to achieve the best fault detection performance for finite field detection performance for finite field multipliers while maintaining a low-complexity implementation, this study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis over GF(2m). The primary concept behind the proposed approach is centered on the implementation of an efficient BCH decoder that utilize Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien-search method to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, a 45-bit multiplicand with five errors has hardware complexity that is only 80%, which is significantly less complex than the most advanced BCH-based fault recognition techniques, such as TMR, Hamming's single error correction, and LDPC-based methods for finite field multiplication which is desirable in constrained applications, such as smart cards, IoT devices, and implantable medical devices.

翻译：有限域乘法器在当代数字系统中应用广泛，其硬件实现的位并行运算通常需要数百万个逻辑门。然而，各种数字设计问题（无论是固有的还是由软错误引起的）都可能导致门电路故障，进而引发乘法器输出结果错误。因此，为了防范错误风险，必须采用具备强大故障检测能力的可靠有限域乘法器实现方案。为了在保持低复杂度实现的同时获得最佳有限域乘法器故障检测性能，本研究针对一种新型位并行多项式基GF(2m)乘法器提出了一种新颖的故障检测方案。所提方法的核心思想在于实现一种高效BCH译码器，该译码器利用Berlekamp-Rumsey-Solomon（BRS）算法和Chien搜索方法，以最小延迟有效定位错误位置。综合结果表明，与现有设计相比，我们针对5位错误45位乘法器提出的错误检测与纠错架构在关键路径延迟上分别减少了37%和49%。此外，当45位被乘数存在5个错误时，其硬件复杂度仅为80%，远低于最先进的基于BCH的故障识别方法（如TMR、汉明单错误纠错和基于LDPC的有限域乘法方法），非常适合智能卡、物联网设备和植入式医疗设备等资源受限的应用场景。