The design space of current quantum computers is expansive with no obvious winning solution. This leaves practitioners with a clear question: "What is the optimal system configuration to run an algorithm?". This paper explores hardware design trade-offs across NISQ systems to guide algorithm and hardware design choices. The evaluation is driven by algorithmic workloads and algorithm fidelity models which capture architectural features such as gate expressivity, fidelity, and crosstalk. We also argue that the criteria for gate design and selection should be extended from maximizing average fidelity to a more comprehensive approach that takes into account the gate expressivity with respect to algorithmic structures. We consider native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, $\sqrt{\text{iSWAP}}$), proposed gates (B Gate, $\sqrt[4]{\text{CNOT}}$, $\sqrt[8]{\text{CNOT}}$), as well as parameterized gates (FSim, XY). Our methodology is driven by a custom synthesis driven circuit compilation workflow, which is able to produce minimal circuit representations for a given system configuration. By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-software co-design for quantum computing.

翻译：当前量子计算机的设计空间极为广阔，但尚无明确的优胜方案。这为实践者留下一个清晰的问题：“运行算法的最佳系统配置是什么？”本文探索了NISQ系统中的硬件设计权衡，以指导算法与硬件设计选择。评估基于算法工作负载与算法保真度模型，这些模型捕捉了门表达能力、保真度及串扰等架构特征。我们还主张，门设计与选择的准则应从最大化平均保真度扩展到更全面的方法，即考虑门相对于算法结构的表达能力。我们研究了原生纠缠门（CNOT、ECR、CZ、ZZ、XX、Sycamore、√iSWAP）、提议门（B门、⁴√CNOT、⁸√CNOT）以及参数化门（FSim、XY）。我们的方法以自定义的合成驱动电路编译工作流为驱动，能够为给定系统配置生成最小电路表示。通过提供评估算法对硬件平台适用性的方法，本文强调了量子计算中硬件-软件协同设计的重要性。