Path planning is critical for autonomous driving, generating smooth, collision-free, feasible paths based on perception and localization inputs. However, its computationally intensive nature poses significant challenges for resource-constrained autonomous driving hardware. This paper presents an end-to-end FPGA-based acceleration framework targeting the quadratic programming (QP), core of optimization-based path planning. We employ a hardware-friendly alternating direction method of multipliers (ADMM) for QP solving and a parallelizable preconditioned conjugate gradient (PCG) method for linear systems. By analyzing sparse matrix patterns, we propose customized storage schemes and efficient sparse matrix multiplication units, significantly reducing resource usage and accelerating matrix operations. Our multi-level dataflow optimization strategy incorporates intra-operator parallelization and pipelining, inter-operator fine-grained pipelining, and CPU-FPGA system-level task mapping. Implemented on the AMD ZCU102 platform, our framework achieves state-of-the-art latency and energy efficiency, including 1.48x faster performance than the best FPGA-based design, 2.89x over an Intel i7-11800H CPU, 5.62x over an ARM Cortex-A57 embedded CPU, and 1.56x over a state-of-the-art GPU solution, along with a 2.05x throughput improvement over existing FPGA-based designs.

翻译：路径规划对于自动驾驶至关重要，它基于感知和定位输入生成平滑、无碰撞且可行的路径。然而，其计算密集型特性给资源受限的自动驾驶硬件带来了重大挑战。本文提出了一种基于FPGA的端到端加速框架，其核心目标是优化基于路径规划的核心——二次规划（QP）。我们采用对硬件友好的交替方向乘子法（ADMM）来求解QP，并采用可并行化的预处理共轭梯度（PCG）法来求解线性系统。通过分析稀疏矩阵模式，我们提出了定制的存储方案和高效的稀疏矩阵乘法单元，从而显著减少了资源使用并加速了矩阵运算。我们的多层次数据流优化策略融合了算子内并行化与流水线、算子间细粒度流水线以及CPU-FPGA系统级任务映射。在AMD ZCU102平台上实现后，我们的框架实现了业界领先的延迟和能效，包括：比最佳的基于FPGA的设计快1.48倍，比Intel i7-11800H CPU快2.89倍，比ARM Cortex-A57嵌入式CPU快5.62倍，比业界领先的GPU解决方案快1.56倍，并且相比现有基于FPGA的设计，吞吐量提升了2.05倍。