Design technology co-optimization (DTCO) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTCO flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process-voltage-temperature (PVT) corners and technology parameters. Validation with 512 unseen technology corners and over one million test data points shows accurate predictions of delay, power, and input pin capacitance for 33 types of cells, with a mean absolute percentage error (MAPE) $\le$ 0.95% and a speed-up of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error $\le$3.0 ps for WNS, percentage errors $\le$0.60% for leakage power, and $\le$0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1-3% improvement.

翻译：设计技术协同优化（DTCO）在实现先进半导体工艺开发的最佳功耗、性能与面积（PPA）中起着关键作用。单元库表征是DTCO流程的核心环节，但传统方法耗时且成本高昂。为应对这些挑战，我们提出一种基于图神经网络（GNN）的机器学习模型，用于快速准确的单元库表征。该模型融合单元拓扑结构，能够在不同工艺-电压-温度（PVT）角点及工艺参数下实现高精度预测。通过512个未见过的工艺角点和超过一百万测试数据点的验证表明，模型对33种单元的延迟、功耗及输入引脚电容的预测平均绝对百分比误差（MAPE）≤0.95%，且相比SPICE仿真实现100倍加速。此外，我们利用GNN模型对未见角点的预测结果，进一步探索了关键系统级指标——最差负时序裕量（WNS）、漏电功耗和动态功耗。与黄金参考值相比，模型对WNS的绝对偏差≤3.0ps，漏电功耗和动态功耗的百分比误差分别≤0.60%和≤0.99%。基于所开发模型，我们进一步提出细粒度驱动强度插值方法，可针对中小规模设计优化PPA，实现约1-3%的性能提升。