Measuring a qubit is a fundamental yet error prone operation in quantum computing. These errors can stem from various sources such as crosstalk, spontaneous state-transitions, and excitation caused by the readout pulse. In this work, we utilize an integrated approach to deploy neural networks (NN) on to field programmable gate arrays (FPGA). We demonstrate that it is practical to design and implement a fully connected neural network accelerator for frequency-multiplexed readout balancing computational complexity with low latency requirements without significant loss in accuracy. The neural network is implemented by quantization of weights, activation functions, and inputs. The hardware accelerator performs frequency-multiplexed readout of 5 superconducting qubits in less than 50 ns on RFSoC ZCU111 FPGA which is first of its kind in the literature. These modules can be implemented and integrated in existing Quantum control and readout platforms using a RFSoC ZCU111 ready for experimental deployment.

翻译：量子比特测量是量子计算中基础但易出错的操作。这些误差可能源于多种因素，例如串扰、自发态跃迁以及读取脉冲引起的激发。本研究采用集成化方法将神经网络部署至现场可编程门阵列上。我们证明，设计并实现一种适用于频率复用读取的全连接神经网络加速器是可行的，该加速器能在计算复杂度与低延迟要求之间取得平衡，且不会造成显著的精度损失。该神经网络通过量化权重、激活函数及输入值实现。该硬件加速器在RFSoC ZCU111 FPGA上以低于50纳秒的延迟完成了5个超导量子比特的频率复用读取，此为文献中首次实现。这些模块可在采用RFSoC ZCU111的现有量子控制与读取平台中实施集成，为实验部署做好准备。