Memory interference may heavily inflate task execution times in Heterogeneous Systems-on-Chips (HeSoCs). Knowing worst-case interference is consequently fundamental for supporting the correct execution of time-sensitive applications. In most of the literature, worst-case interference is assumed to be generated by, and therefore is estimated through read-intensive synthetic workloads with no caching. Yet these workloads do not always generate worst-case interference. This is the consequence of the general results reported in this work. By testing on multiple architectures, we determined that the highest interference generation traffic pattern is actually hardware dependant, and that making assumptions could lead to a severe underestimation of the worst-case (in our case, of more than 9x).

翻译：内存干扰可能会严重增加异构系统芯片（HeSoCs）中任务的执行时间。因此，了解最坏情况下的干扰对于支持时间敏感型应用的正确执行至关重要。在现有文献中，最坏情况下的干扰通常假设由无缓存的读密集型合成工作负载产生，并通过此类工作负载进行估算。然而，这些工作负载并不总是能触发最坏情况下的干扰。这是本研究报告的普适性结论所导致的后果。通过在多种架构上进行测试，我们确定最高干扰生成流量模式实际上依赖于硬件，而基于假设的估算可能导致对最坏情况的严重低估（在我们的案例中，低估程度超过9倍）。