Open-source 5G and O-RAN experimentation now spans discrete-event simulators, host-OS emulators, SDR hardware-in-the-loop testbeds, O-RU/Open Fronthaul deployments, wireless digital twins, and accelerator-backed RAN runtimes. These environments may expose similar protocol interfaces while preserving very different timing, I/O, synchronization, buffering, transport, and observability behavior. Thus, studies that appear to measure the same network property may instead measure different execution harnesses: functional compatibility is not timing fidelity. This paper presents AtlasRAN, a timing-aware evaluation framework for deciding what an open-source 5G platform can credibly measure. AtlasRAN provides two reference architectures: a CPU-centric path spanning software emulation, SDR/HIL, and O-RU/OFH execution, and an accelerator/twin path spanning offline modeling, code-realistic twins, and real-time AI-RAN runtimes, plus a compact claim-to-capability matrix. We ground the framework in a CU--DU uplink load study comparing OpenAirInterface RFSim with the Sionna Research Kit, which offloads LDPC decoding to CUDA while retaining much of the surrounding OAI host-OS emulation path. As UE concurrency increases, OAI goodput falls from 114.59 Mb/s at one UE to 16.35 Mb/s in the degraded twelve-UE region, while Sionna-RK falls from 103.34 Mb/s to 16.15 Mb/s. Fairness remains near ideal, CPU/GPU utilization falls with load, and the RFSim real-time factor drops below unity, indicating that the accelerated decoder is under-fed by host-OS inter-process communication and timing effects rather than saturated. AtlasRAN therefore argues that integrated wireless testbeds and digital twins should report timing discipline, transport path, memory movement, and observability as first-class experimental variables.

翻译：开源5G与O-RAN实验现已涵盖离散事件模拟器、主机操作系统仿真器、软件无线电硬件在环测试平台、O-RU/开放前传部署、无线数字孪生体以及加速器支撑的RAN运行时环境。这些环境可能暴露类似的协议接口，但保留迥异的时序、输入/输出、同步、缓冲、传输与可观测性行为。因此，看似测量相同网络属性的研究可能实际在测量不同的执行框架：功能兼容性不等于时序保真度。本文提出AtlasRAN，一个用于判定开源5G平台可可信测量内容的时序感知评估框架。AtlasRAN提供两种参考架构：一条以CPU为中心路径，涵盖软件仿真、SDR/HIL与O-RU/OFH执行；另一条加速器/孪生体路径，涵盖离线建模、代码真实孪生体与实时AI-RAN运行时，外加一个紧凑的声明-能力矩阵。我们将该框架应用于一项CU-DU上行负载研究，对比了OpenAirInterface RFSim与Sionna Research Kit——后者将LDPC解码卸载至CUDA，同时保留大部分外围OAI主机操作系统仿真路径。随着UE并发数增加，OAI吞吐率从单个UE时的114.59 Mb/s降至12个UE退化区域时的16.35 Mb/s，而Sionna-RK从103.34 Mb/s降至16.15 Mb/s。公平性保持接近理想状态，CPU/GPU利用率随负载下降，RFSim实时因子降至1以下，表明加速解码器受主机操作系统进程间通信与时序效应而非饱和状态导致的输入不足。因此，AtlasRAN主张一体化无线测试平台与数字孪生体应将时序纪律、传输路径、内存移动与可观测性作为一等实验变量进行报告。