Floating random walk-based capacitance extraction has emerged in recent years as a tried and true approach for extracting parasitic capacitance in very large scale integrated circuits. Being a Monte Carlo method, its performance is dependent on the variance of sampled quantities and variance reduction methods are crucial for the challenges posed by ever denser process technologies and layout-dependent effects. In this work, we present a novel, universal variance reduction method for floating random walk-based capacitance extraction, which is conceptually simple, highly efficient and provably reduces variance in all extractions, especially when layout-dependent effects are present. It is complementary to existing mathematical formulations for variance reduction and its performance gains are experienced on top of theirs. Numerical experiments demonstrate substantial such gains of up to 50% in number of walks necessary as well as in actual extraction times compared to the best previously proposed variance reduction approaches for the floating random-walk.

翻译：近年来，基于浮动随机游走的电容提取已成为超大规模集成电路中寄生电容提取的成熟可靠方法。作为蒙特卡洛方法，其性能取决于采样量的方差，而针对日趋密集的工艺技术与版图相关效应带来的挑战，方差缩减方法至关重要。本文提出一种新型通用方差缩减方法，用于浮动随机游走电容提取，该方法概念简洁、高效且可证明在所有提取中（尤其存在版图相关效应时）均能降低方差。该方法与现有方差缩减数学公式互补，可在其基础上进一步提升性能。数值实验表明，与先前提出的最佳浮动随机游走方差缩减方法相比，本方法在所需步数及实际提取时间上均实现显著增益，最高可达50%。