Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an increase in embodied emissions, encompassing carbon emissions arising from design, manufacturing, packaging, and other infrastructural activities. While existing research has developed tools to analyze embodied carbon at the computer architecture level for traditional monolithic systems, these tools do not apply to near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential for sustainable computing by minimizing carbon emissions through two key strategies: ``reducing" computation by reusing pre-designed chiplet IP blocks and adopting hierarchical approaches to system design. The reuse of chiplets across multiple designs, even spanning multiple generations of integrated circuits (ICs), can substantially reduce embodied carbon emissions throughout the operational lifespan. This paper introduces a carbon analysis tool specifically designed to assess the potential of HI systems in facilitating greener VLSI system design and manufacturing approaches. The tool takes into account scaling, chiplet and packaging yields, design complexity, and even carbon overheads associated with advanced packaging techniques employed in heterogeneous systems. Experimental results demonstrate that HI can achieve a reduction of embodied carbon emissions up to 70\% compared to traditional large monolithic systems. These findings suggest that HI can pave the way for sustainable computing practices, contributing to a more environmentally conscious semiconductor industry.

翻译：数十年来，能效与低功耗设计的进步已成功降低了半导体行业的运行碳足迹。然而，这也导致隐含碳排放的增加，其范围涵盖设计、制造、封装及其他基础设施活动产生的碳排放。现有研究虽已开发出在计算机架构层面分析传统单片系统隐含碳足迹的工具，但这些工具并不适用于即将成为主流的异构集成技术。异构集成系统通过两大关键策略实现可持续计算：其一是通过复用预设计的芯粒知识产权模块"减少"计算开销，其二是采用层级化系统设计方法。芯粒在多个设计中乃至跨代集成电路的复用，可显著降低全生命周期隐含碳排放。本文提出一款专用于评估异构集成系统在推动绿色超大规模集成电路设计与制造方法潜力的碳分析工具。该工具综合考虑了缩放效应、芯粒与封装良率、设计复杂度，甚至包括异构系统中先进封装技术带来的碳开销。实验结果表明，相较传统大型单片系统，异构集成可减少最高70%的隐含碳排放。这些发现表明异构集成技术可为可持续计算实践铺平道路，助力打造更具环保意识的半导体产业。