This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.

翻译：本文报告了一种名为微型中值滤波器的小型硅资源占用、高度灵活的任意百分位查找方案的设计、实现与测试。该方案不仅可用于具有方形滤波窗口的图像处理中值滤波，还可应用于任意尺寸数据集的任意百分位滤波或最大值/最小值查找，只要数据的比特位数有限。它为使用非方形或不规则滤波窗口的图像处理任务提供了可能性。在此方案中，避免了数据交换或数据位操作，并通过应用逻辑组件的高功能效率来节省硅资源。部分逻辑功能被吸收到其他功能中，以进一步降低复杂度。组合逻辑路径被设计得足够短，使得固件能够编译至FPGA器件块存储器所允许的最高工作频率。微型中值滤波器以不间断方式接收、处理和输出数据，且无不规则时序，这有助于简化周边级的设计。