Systolic arrays are a prominent choice for deep neural network (DNN) accelerators because they offer parallelism and efficient data reuse. Improving the reliability of DNN accelerators is crucial as hardware faults can degrade the accuracy of DNN inferencing. Systolic arrays make use of a large number of processing elements (PEs) for parallel processing, but when one PE is faulty, the error propagates and affects the outcomes of downstream PEs. Due to the large number of PEs, the cost associated with implementing hardware-based runtime monitoring of every single PE is infeasible. We present a solution to optimize the placement of hardware monitors within systolic arrays. We first prove that $2N-1$ monitors are needed to localize a single faulty PE and we also derive the monitor placement. We show that a second placement optimization problem, which minimizes the set of candidate faulty PEs for a given number of monitors, is NP-hard. Therefore, we propose a heuristic approach to balance the reliability and hardware resource utilization in DNN accelerators when number of monitors is limited. Experimental evaluation shows that to localize a single faulty PE, an area overhead of only 0.33% is incurred for a $256\times 256$ systolic array.

翻译：脉动阵列是深度神经网络（DNN）加速器的优选架构，因其具备并行处理能力和高效数据复用特性。提升DNN加速器的可靠性至关重要，因为硬件故障可能降低DNN推理的精度。脉动阵列采用大量处理单元（PE）实现并行计算，但当一个PE发生故障时，错误会传播并影响下游PE的计算结果。由于PE数量庞大，为每个PE部署基于硬件的运行时监测所产生的成本不可接受。本文提出一种优化脉动阵列中硬件监测点布局的解决方案。首先证明需要$2N-1$个监测点才能定位单个故障PE，并推导出监测点的具体布局方案。进一步表明，在给定监测点数量条件下最小化候选故障PE集合的二次布局优化问题是NP难的。为此，我们提出一种启发式方法，在监测点数量受限时平衡DNN加速器的可靠性与硬件资源利用率。实验评估表明，针对$256\times 256$规模的脉动阵列，定位单个故障PE仅需0.33%的面积开销。