Multi-chiplet GPUs split memory into local and remote HBM regions across a silicon interposer, and reducing the remote HBM traffic is crucial for the performance and energy efficiency of multi-chiplet GPUs. For general matrix multiplication (GEMM), the dominant operator in large language models (LLMs), the resulting inter-chiplet traffic depends strongly on kernel choices such as operand layout, CTA traversal order, and data placement, and the optimal strategy to minimize remote accesses is nontrivial. We present a fast, functional, tile-level locality simulator that models CTA scheduling, per-chiplet L2 caches, and local/remote HBM accesses to evaluate a full-size LLM GEMM configuration. Across representative LLM GEMMs, the simulator shows that remote traffic varies by up to 90x across the design space for the same GEMM dimensions. Moreover, using the simulator as feedback, an agentic AI discovers that a 2D block-swizzle CTA traversal reduces remote traffic over the best 1D traversal by up to 5.1x under round-robin placement, identifying CTA traversal order as a first-order, GEMM-dependent design knob for inter-chiplet traffic.

翻译：多芯粒GPU通过硅中介层将存储器划分为本地与远程HBM区域，降低远程HBM流量对于提升多芯粒GPU的性能和能效至关重要。针对大语言模型中的核心算子——通用矩阵乘法（GEMM），其产生的芯粒间流量高度依赖于内核选择（如操作数布局、CTA遍历顺序和数据放置方式），因此最小化远程访问的最优策略具有非平凡性。我们提出了一种快速、功能性的瓦片级局部性模拟器，该模拟器通过建模CTA调度、每芯粒L2缓存以及本地/远程HBM访问，可评估全尺寸LLM GEMM配置。在代表性LLM GEMM测试中，该模拟器表明：对相同GEMM维度而言，设计空间内的远程流量差异可达90倍。此外，通过将该模拟器作为反馈，自主智能体发现：在轮询放置策略下，二维块交织CTA遍历相比最优一维遍历可将远程流量降低至多5.1倍，证明了CTA遍历顺序是芯粒间流量中一阶且依赖GEMM特性的设计调控因子。