Triggerless Data Acquisition Systems (DAQs) require transmitting the data stream from multiple links to the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g. PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO)for high-speed data routing.A thorough analysis of the network operation enabled increased scalability compared to the previously published concentrator based on 8x8 network. The presented solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were done for 4 and 5 layers (16 and 32 inputs). The FPGA synthesis has been performed for 16inputs. The pipeline registers may be added in each network independently, shortening the critical path and increasing the maximum acceptable clock frequency.

翻译：无触发数据采集系统（DAQ）要求将来自多链路的数据流传输至处理节点。短输入数据字必须被集中并封装为输出接口（如PCI Express）所使用的较长位向量。在此过程中，需剔除无效数据并生成稠密的有用DAQ数据流，同时保持数据的时间顺序。本文提出一种采用反向输出基线网络（BNRO）的新型高速数据路由解决方案。通过对网络操作的深入分析，相较于此前基于8×8网络的数据集中器，本方案实现了更高的可扩展性。通过向BNRO网络添加额外层，可在最小化资源消耗的同时扩展该方案。针对4层与5层结构（16输入与32输入）进行了仿真实验，并对16输入配置完成了FPGA综合。各网络层可独立添加流水线寄存器，以缩短关键路径并提升最大可接受时钟频率。