The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether natural or stemming from soft errors, can result in gate malfunction, ultimately leading to erroneous multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ an effective finite field multiplier implementation that boasts a robust fault detection capability. This study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), intended to achieve optimal fault detection performance for finite field multipliers while simultaneously maintaining a low-complexity implementation, a favored attribute in resource-constrained applications like smart cards. The primary concept behind the proposed approach is centered on the implementation of a BCH decoder that utilizes re-encoding technique and FIBM algorithm in its first and second sub-modules, respectively. This approach serves to address hardware complexity concerns while also making use of Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien search method in the third sub-module of the decoder to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, the hardware complexity associated with a 45-bit multiplicand that contains 5 errors is confined to a mere 80%, which is significantly lower than the most exceptional BCH-based fault recognition methodologies, including TMR, Hamming's single error correction, and LDPC-based procedures within the realm of finite field multiplication.

翻译：有限域乘法器在现代数字系统中应用广泛，其位并行运算的硬件实现通常需要数百万个逻辑门。然而，各种数字设计问题（无论是自然原因还是由软错误引发）可能导致门电路故障，最终造成乘法器输出错误。因此，为降低对错误的敏感性，必须采用具有强大故障检测能力的有效有限域乘法器实现方案。本研究针对一种新型的基于GF(2m)的位并行多项式基乘法器，提出了一种新颖的故障检测方案，旨在实现有限域乘法器的最优故障检测性能，同时保持低复杂度实现——这一特性在智能卡等资源受限应用中备受青睐。所提方法的核心思路是采用BCH解码器实现，其第一子模块和第二子模块分别运用重编码技术和FIBM算法。该方法在解码器第三子模块中结合Berlekamp-Rumsey-Solomon（BRS）算法与Chien搜索方法，以最小延迟有效定位错误，同时解决硬件复杂度问题。综合结果表明，针对支持5位错误校正的45位乘法器，所提错误检测与校正架构的关键路径延迟较现有设计降低了37%和49%。此外，当被乘数为45位且包含5位错误时，其硬件复杂度仅维持在80%，显著低于有限域乘法领域中基于BCH的顶尖故障识别方法（包括TMR、汉明单错误校正及LDPC方法）。