Front-end electronics equipped with high-speed digitizers are being used and proposed for future nuclear detectors. Recent literature reveals that deep learning models, especially one-dimensional convolutional neural networks, are promising when dealing with digital signals from nuclear detectors. Simulations and experiments demonstrate the satisfactory accuracy and additional benefits of neural networks in this area. However, specific hardware accelerating such models for online operations still needs to be studied. In this work, we introduce PulseDL-II, a system-on-chip (SoC) specially designed for applications of event feature (time, energy, etc.) extraction from pulses with deep learning. Based on the previous version, PulseDL-II incorporates a RISC CPU into the system structure for better functional flexibility and integrity. The neural network accelerator in the SoC adopts a three-level (arithmetic unit, processing element, neural network) hierarchical architecture and facilitates parameter optimization of the digital design. Furthermore, we devise a quantization scheme compatible with deep learning frameworks (e.g., TensorFlow) within a selected subset of layer types. We validate the correct operations of PulseDL-II on field programmable gate arrays (FPGA) alone and with an experimental setup comprising a direct digital synthesis (DDS) and analog-to-digital converters (ADC). The proposed system achieved 60 ps time resolution and 0.40% energy resolution at signal to noise ratio (SNR) of 47.4 dB.

翻译：配备高速数字化仪的前端电子学系统正被应用于未来核探测器。最新研究表明，深度学习模型（尤其是一维卷积神经网络）在处理核探测器数字信号时展现出显著优势。仿真与实验验证了神经网络在该应用中的高精度及附加价值，但针对实时运算的专用硬件加速器仍需深入研究。本文提出PulseDL-II——专为基于深度学习的脉冲事件特征（时间、能量等）提取而设计的片上系统（SoC）。相较早期版本，PulseDL-II在系统架构中集成了RISC CPU以实现更优的功能灵活性与完整性。该SoC内的神经网络加速器采用三级层次架构（运算单元→处理单元→神经网络），并支持数字设计参数优化。此外，我们设计了一种兼容深度学习框架（如TensorFlow）的量化方案，适用于选定子集的层类型。我们通过独立现场可编程门阵列（FPGA）实验与包含直接数字合成器（DDS）及模数转换器（ADC）的联合实验平台，验证了PulseDL-II的功能正确性。在信噪比（SNR）为47.4 dB条件下，该系统实现了60 ps时间分辨率与0.40%能量分辨率。