Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA- SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems.

翻译：模拟退火（SA）是解决组合优化问题的经典算法。然而，随着问题规模的增大，SA的计算时间会急剧增加。近期，一种收敛速度优于传统SA的随机模拟退火（SSA）算法被提出。本文提出一种面向硬件优化的SSA（HA-SSA）算法，旨在实现内存高效的现场可编程门阵列（FPGA）部署。HA-SSA能够在保持SSA计算速度的同时，显著降低存储中间结果的内存开销。为进行评估，所提算法在最大割组合优化问题上与传统SSA及SA方法进行了对比实验。在G-set（最大割问题数据集）中选取不同规模问题时，HA-SSA的收敛速度最高可达传统SA算法的114倍。该算法在FPGA平台（Xilinx Kintex-7）上实现后，在保持优化问题求解质量的同时，内存效率最高可达到传统SSA的6倍。