Probabilistic bits (p-bits) offer an energy-efficient hardware abstraction for stochastic optimization; however, existing p-bit-based simulated annealing accelerators suffer from poor scalability and limited support for fully connected graphs due to fan-out and memory overhead. This paper presents an energy-efficient FPGA architecture for stochastic simulated quantum annealing (SSQA) that addresses these challenges. The proposed design combines a spin-serial and replica-parallel update schedule with a dual-BRAM delay-line architecture, enabling scalable support for fully connected Ising models while eliminating fan-out growth in logic resources. By exploiting SSQA, the architecture achieves fast convergence using only final replica states, significantly reducing memory requirements compared to conventional p-bit-based annealers. Implemented on a Xilinx ZC706 FPGA, the proposed system solves an 800-node MAX-CUT benchmark and achieves up to 50% reduction in energy consumption and over 90\% reduction in logic resources compared with prior FPGA-based p-bit annealing architectures. These results demonstrate the practicality of quantum-inspired, p-bit-based annealing hardware for large-scale combinatorial optimization under strict energy and resource constraints.

翻译：概率比特（p-bit）为随机优化提供了节能的硬件抽象；然而，现有的基于p比特的模拟退火加速器由于扇出和内存开销，存在可扩展性差和对全连接图支持有限的问题。本文提出了一种用于随机模拟量子退火（SSQA）的节能型FPGA架构，以应对这些挑战。所提出的设计将自旋串行与副本并行更新调度相结合，并采用双BRAM延迟线架构，从而在消除逻辑资源中扇出增长的同时，实现了对全连接伊辛模型的可扩展支持。通过利用SSQA，该架构仅使用最终副本状态即可实现快速收敛，与传统的基于p比特的退火器相比，显著降低了内存需求。在Xilinx ZC706 FPGA上实现的系统解决了800节点的MAX-CUT基准问题，与先前的基于FPGA的p比特退火架构相比，能耗降低高达50%，逻辑资源减少超过90%。这些结果证明了在严格的能耗和资源约束下，量子启发的、基于p比特的退火硬件在大规模组合优化中的实用性。