Modern technology-independent logic synthesis has been developed to optimize for the size and depth of AND-Inverter Graphs (AIGs) as a proxy of CMOS circuit area and delay. However, for non-CMOS-based emerging technologies, AIG size and depth may not be good cost estimations. Dedicated algorithms optimizing for more complex cost functions have been proven effective for their specific target applications yet require time and experts in both logic synthesis and the targeted technology to develop. In this work, we propose AnySyn, a cost-generic optimization framework for agile experimentation and prototyping of various customized cost functions before investing in developing specialized algorithms. Experimental results show that AnySyn outperforms non-specialized size and depth optimization algorithms by 14% and 19% on average and achieves comparable results to specialized algorithms within acceptable CPU time.

翻译：现代工艺无关的逻辑综合已被开发用于优化与逆变器图（AIG）的尺寸和深度，以作为CMOS电路面积和延迟的代理指标。然而，对于基于非CMOS的新兴技术，AIG尺寸和深度可能并非良好的代价估计。针对更复杂代价函数的专用算法已被证明对特定目标应用有效，但其开发需要同时精通逻辑综合和目标技术的领域专家及时间投入。本文提出AnySyn这一通用代价优化框架，可在开发专用算法之前快速进行多种自定义代价函数的敏捷实验与原型验证。实验结果表明，AnySyn相比非专用的尺寸和深度优化算法平均提升14%和19%，且在可接受的CPU时间内能达到与专用算法相当的性能。