The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann bottleneck by performing computation in or near memory. An inevitability of transferring neural networks onto hardware is that non-idealities such as device-to-device variations or poor device yield impact performance. Methods such as hardware-aware training, where substrate non-idealities are incorporated during network training, are one way to recover performance at the cost of solution generality. In this work, we demonstrate inference on hardware neural networks consisting of 20,000 magnetic tunnel junction arrays integrated on a complementary metal-oxide-semiconductor chips that closely resembles market-ready spin transfer-torque magnetoresistive random access memory technology. Using 36 dies, each containing a crossbar array with its own non-idealities, we show that even a small number of defects in physically mapped networks significantly degrades the performance of networks trained without defects and show that, at the cost of generality, hardware-aware training accounting for specific defects on each die can recover to comparable performance with ideal networks. We then demonstrate a robust training method that extends hardware-aware training to statistics-aware training, producing network weights that perform well on most defective dies regardless of their specific defect locations. When evaluated on the 36 physical dies, statistics-aware trained solutions can achieve a mean misclassification error on the MNIST dataset that differs from the software-baseline by only 2 %. This statistics-aware training method could be generalized to networks with many layers that are mapped to hardware suited for industry-ready applications.

翻译：随着支持更复杂应用所需的神经网络规模不断扩大，对面积和能效优化硬件的需求日益增加。满足这类应用资源预算的途径之一是通过在存储介质内部或附近执行计算来规避冯·诺依曼瓶颈。将神经网络部署到硬件时不可避免的问题在于，器件间差异或低良率等非理想特性会严重影响性能。硬件感知训练（即在网络训练过程中融入基底非理想特性）是一种以牺牲解决方案通用性为代价来恢复性能的方法。本研究在集成20,000个磁隧道结阵列的互补金属氧化物半导体芯片上演示了硬件神经网络的推理，该芯片与即将量产的自旋转移矩磁随机存取存储器技术高度相似。利用36个具有各自非理想特性的交叉阵列晶粒，我们证明物理映射网络中即使少量缺陷也会显著降低无缺陷训练网络的性能，同时表明以通用性为代价，针对各晶粒特定缺陷的硬件感知训练可使性能恢复至与理想网络相当的水平。随后我们展示了一种鲁棒训练方法，将硬件感知训练扩展为统计感知训练，生成的网络权重在大多数有缺陷晶粒上均能表现良好，无论其缺陷位置如何。在36个物理晶粒上的评估显示，统计感知训练方案在MNIST数据集上的平均误分类率与软件基线仅差2%。这种统计感知训练方法可推广至适用于工业级应用的多层硬件映射网络。